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RESEARCH ON INTEGRATED CIRCUITS OF MODERN NANOTECHNOLOGY

The progress in microelectronics increases the potential of digital integrated circuits, but at the same time it also increases the level of difficulty of testing their proper function.

Digital memories are no exception to this rule. The difficulty of testing modern, digital memories is largely due to the fact that the dimensions of the elementary storage units, known as memory cells, continuously become smaller and smaller. The interaction between these memory cells thus results to the interference of the operation of the digital memory.

Mr. Yiorgos Sfikas, PhD candidate of the University of Ioannina and Mr. Yiorgos Tsarouchas, Associate Professor of the University of Ioannina, have carried out a research study in order to reduce the cost of testing compared to the Neighborhood Pattern Sensitive Fault model - NPSF, as far as integrated memory circuits in modern Nanometer technology are concerned, and won the "Best Paper Award" by DDECS, in 2009.

New algorithms debugger for digital memories

TESTING AND DESIGNING MODELS

The NPSF model is a general fault model for all memory types. Its aim is to identify “small” defects in memory, which can cause false response under very specific circumstances. Although it is recognized as a high quality fault model in covering defects compared to other memory fault models, the very high cost for its application, restricts its wide adoption by the semiconductor industry.

To overcome this problem the physical design (layout) and structure of modern memory arrays was used to introduce a new neighborhood type (the Δ-Type neighborhood) for NPSF testing along with appropriate faults detection and tracking algorithms. The test cost was reduced drastically, about 58%, with respect to the well known Type-1 neighborhood. In addition, a new fault model was introduced, the Neighborhood Word line Sensitive Fault mode (NSFW) and there were developed methods for fault detection produced in combination with NPSF faults.

In a future extension of this study, the design of an incorporated self test circuit could be made (Built-In Self Test - BIST) which will implement one or more of the proposed algorithms and it will provide the ability of testing the DRAM memories. A second possible direction for future work is the effort to reduce the cost of the proposed algorithms further.

Design and Diagnostics of Electronic Circuits and Systems – DDECS, 2009

The research paper "Physical Design Oriented DRAM Neighborhood Pattern Sensitive Fault Testing" by Yiorgos Sfikas, PhD candidate and Yiorgos Tsiatouchas, Associate Professor, University of Ioannina, received the "Best Paper Award" award in the DDECS symposium where held in April 2009 in the Czech Republic.

DDECS provides a forum for exchanging ideas, discussing research results, and presenting practical applications in the areas of design, test, and diagnosis of electronic circuits and systems.

UNIVERSITY OF IOANNINA

Yiorgos Sfikas, PhD Candidate, Department of Computer Science & Engineering , University of Ioannina.

Yiorgos Tsiatouhas, Associate Professor, Department of Computer Science & Engineering, University of Ioannina.

http://ddecs2009.tul.cz/ http://cs.uoi.gr/en/index.php?menu=m1